Efficient Design of QCA Adder Structures

Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high-performance QCA computers in this emerging nano-technological paradigm. In this paper, we demonstrate that QCA ripple carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs because of the increase in required interconnects. Simulation results obtained by using the QCADesigner tool for the proposed adder designs are also presented. Introduction Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching its limit after decades of exponential growth. This has prompted the development of many nano-scale molecular devices [1]. Quantum-dot cellular automata (QCA) is one promising emerging nanotechnological paradigm. Initially developed by Prof. Craig Lent at the University of Notre Dame, QCA performs computation not on electron flow but on Coulombic interactions of electrons trapped in quantum dots [2]. The properties of extremely high density, low power, and potentially high processing speed make QCA one of the most attractive alternatives for CMOS. At the IEEE ISCAS 2004 conference, QCA was identified as a promising research area for the CAS and VLSI societies. Although a scalable physical realization of QCA for high speed computing has not emerged, some experimental devices and circuits have been created as a proof of concept [1-3]. QCA devices have been fabricated and tested based on metal dots on an oxidized silicon substrate [1-3]. The operating temperatures for these devices were approximately 80mK. Also, molecular QCA devices (1~10nm) are being explored, and are predicted to operate at room temperature. Circuits using molecular QCA can be built at an estimated density of up to 1013 devices per cm2, and operated as fast as 2.5THz with a theoretical maximum of 25THz. QCA is currently being studied in both devices and circuits level. This paper focuses on the QCA circuit design and analysis, which is one of the fundamental parts in QCA research. Similar to CMOS, QCA circuit optimizations are targeting high-speed and area-efficient design. Since QCA devices such as wires, gates are based on QCA cells rather than CMOS transistor, QCA circuit requires different design methodologies compared to CMOS design. In this paper, we first summarize the design techniques of QCA clocking and interconnect. Recent theoretical work suggested clocked control of QCA circuitry by periodically modulating interdot barriers, in which the design speed is determined completely by the clocking. Also, we found out that QCA coplanar crossover is not reliable. Thus, we suggest that a multi-layer QCA interconnect structure could be used. The multi-layer interconnect can reduce the total area required to implement a circuit. This study is importance for many QCA circuit designs. Using the clocking and interconnect techniques, we then carry out a study to obtain efficient QCA adders in this paper. Unlike standard CMOS technologies that often benefit from parallel architectures, QCA technology is differentiated by its fine pipelining and multiple clocking zones, which benefit more from classical serial techniques. QCA Circuit Architectures QCA Basics. The operation of a QCA cell has been demonstrated experimentally in a four-dot system, which is based on the interaction of bi-stable QCA cells constructed from four quantum dots. The cell is charged with two electrons, which are free to tunnel between adjacent dots. These electrons tend to occupy antipodal sites as a result of their mutual electrostatic repulsion. Thus, there exist two equivalent energetically minimal arrangements of the two electrons in the QCA cell as shown in Fig. (1a). These two arrangements can represent logic ‘1’ and ‘0’ respectively so that binary information can be encoded. Solid State Phenomena Vols. 121-123 (2007) pp 553-556 online at http://www.scientific.net © (2007) Trans Tech Publications, Switzerland Online available since 2007/Mar/15 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of the publisher: Trans Tech Publications Ltd, Switzerland, www.ttp.net. (ID: 130.203.133.33-16/04/08,09:51:38) The basic logic gate in QCA is the majority gate. It can be realized with 5 QCA cells, as shown in Fig. (1b). Assuming the inputs are A, B and C, the logic function of a majority gate is ( , , ) M A B C AB AC BC = + + (1). Then, logic AND and OR functions can be implemented from a majority gate by setting one input permanently to ‘0’ or ‘1’, respectively. Along with the inverter, the majority gate forms a universal logic set and can be used to implement any logic function. (a) QCA cell (b) QCA majority gate Figure 1. QCA cell and majority gate. QCA Clocking. QCA clocking controls information flow around the circuit and it also enables power gain in QCA devices. Moreover, clocking can avoid the problem that the QCA array may not settle in its energetically minimal state when the inputs are switched abruptly. A physical schematic of a QCA clocking system is shown in Fig. 2. A single surface of QCA cells is located in the x-axis and a series of buried wires run in the z direction underneath them. Voltages applied to the wires produce an electric field at the QCA surface that affects the cells activity state (latched, relaxed, or switching). Figure 2. A large-scale, clocked, molecular QCA array. Figure 3. QCA clocking zones. The QCA surface, containing a line of QCA cells, is found on the x axis. Wires buried under this surface run perpendicular to the page and induce an electric field at the QCA surface when a voltage is applied to them. The electric field in the ŷ direction influences the cell’s state: latched, relaxed, or switching; and not its polarization: ‘1’ or ‘0’, which will be determined by the cell’s neighbor. The voltage signals on the wires are periodic and adjacent wires have a π/2 phase shift between them, so that every fourth wire will have the same applied signal. Fig. 3 shows the voltage signals on four adjacent wires, which are referred to as the four-phase clocking signal (clocking zones). The signal on the buried wires will induce a roughly sinusoidal clocking electric field that propagates across the QCA surface so as to control the information flow over QCA cells. QCA D-Latches. Voltages applied to the wires produce an electric field at the QCA surface that affects the cells activity state (latched, relaxed, or switching). When the clock signal is low the cell is latched. When the clock signal is high the cell is relaxed and has no polarization. In between these states the cell is either latched or relaxed (switching), entirely determined by its neighbors. Since the cells in one clocking zone become latched and remain latched until the next group of cells is latched, they can be considered as comprising a D-latch . For example, a clocked QCA wire is shown in Fig. 4. If C0, C1, C2 and C3 (different shades of gray) denote the four clocking zones of a clock cycle, then, cells D0, D1, D2 and D3 will be considered as a series of D-latches. QCA Latency. If a section of the wire is replaced with a majority gate having the same clocking zone, as shown in Fig. 5, adding the majority gate does not increase the delay, or clocking latency, of the wire compared to that without a majority gate. In QCA, the design speed is determined completely by the largest number of clocking zones between input and output. We will refer to delay in terms of clocking latency, since the number of clocking zones between two signal points dominates the delay. Minimizing the number of clocking zones leads to a better design. Although majority gates themselves do not directly increase the clocking latency, interconnects which associated with connecting each majority gate together do increase the overall latency. Therefore a design that consists of fewer gates will, in most cases, requires less interconnects and therefore has lower overall latency. 554 Nanoscience and Technology